1. Technical Field
The present invention relates to a shift register, a scanning-line drive circuit, a data-line drive circuit, an electro-optical device, and an electronic apparatus.
2. Related Art
Electro-optical devices that perform display by utilizing liquid crystals or organic electronic-luminescence (EL) are widely known. In such an electro-optical device, a scanning-line drive circuit includes a shift register and generates scanning signals for sequentially selecting a plurality of scanning lines. Some of such shift registers include transistors having the same conductivity type and operate in response to two-phase clock signals. An example of such shift registers is disclosed in Japanese Patent No. 4,083,581.
FIG. 13 is a block diagram illustrating the configuration of a shift register 200 operating in response to two-phase clock signals. When a start pulse signal STV is input to a first unit circuit 210-1, the shift register 200 sequentially shifts and outputs output signals G.
FIG. 14 is a circuit diagram illustrating an example of the configuration of a unit circuit 210. The unit circuit 210 includes, as shown in FIG. 14, a pull-up transistor PUTr, a pull-down transistor PDTr, a capacitor C1, and a nodeA controller 212. The nodeA controller 212 includes transistors Tr3 and Tr4 and controls the potential of the gate (hereinafter referred to as the “nodeA”) of the pull-up transistor PUTr.
FIG. 15 is a timing chart illustrating the operation of the unit circuit 210. The period F1 is the initial state in which the pull-up transistors PUTr and the pull-down transistor PDTr are OFF.
At time t1, an inverted clock signal CLKB shifts from a low level to a high level to turn ON the pull-down transistor PDTr. Then, a power supply potential VGL is supplied to one terminal of the capacitor C1. At this time, the start pulse signal STV or an output signal G(n−1) of the previous unit circuit 210-(n−1) is at a high level so that the transistor Tr4 is turned ON. Accordingly, a current is supplied to the other terminal of the capacitor C1 so that charging of the capacitor C1 is started. Then, the potential of the nodeA increases. At this stage, the potential of the nodeA exceeds the threshold voltage of the pull-up transistor PUTr so that the pull-up transistor PUTT is turned ON.
Then, at time t2, the start pulse signal STV or the output signal G(n−1) of the previous unit circuit 210-(n−1) is made to have a low level so that the transistor Tr4 is turned OFF. The inverted clock signal CLKB is also made to have a low level, causing the pull-down transistor PDTr to turn OFF. At this time, since the potential of the nodeA exceeds the threshold of the pull-up transistor PUTr, the pull-up transistor PUTr remains in the ON state. Since the clock signal CLK is at a high level at time t2, the potential of an output terminal OT increases. Then, the potential of the nodeA rises due to bootstrapping to such a degree that it exceeds the high level of the clock signal CLK. This makes it possible to match the high level of the output signal G(n) to that of the clock signal CLK.
Then, at time t3, the inverted clock signal CLKB is made to have a high level so that the pull-down transistor PDTr is turned ON. Then, the output signal G(n) is made to have a low level. The output signal G(n+1) of the subsequent unit circuit 210-(n+1) is input as a control signal to the unit circuit 210(n) so that the transistor Tr3 is turned ON. This starts the discharging of the capacitor C1 so that the potential of the nodeA is made to have a low level.
In one cycle of the shift operations of the shift register 200, the pull-up transistor PUTr performs, as shown in FIG. 15, one ON/OFF operation to change the output signal G(n) to a high level. In contrast, the pull-down transistor PDTr repeats the ON/OFF operations in synchronization with the inverted clock signal CLKB. Additionally, the period during which the pull-down transistor PDTr is ON is longer than that during which the pull-up transistor PUTr is ON. This causes the deterioration of the pull-down transistor PDTr to occur more rapidly than the pull-up transistor PUTT.
The deterioration of the pull-down transistor PDTr increases the ON resistance of the pull-down transistor PDTr. The potential of the output signal G(n) changes in response to a time constant given by, for example, a load connected to the output terminal OT or the ON resistance of the pull-down transistor PDTr. The increased ON resistance due to the deterioration over time induces the following phenomenon. When the pull-down transistor PDTr is turned ON at time t3, the output signal G(n) does not drop immediately to a low level, thereby causing rounding of the falling edge of the output signal G(n), as indicated by the dotted lines shown in FIG. 15. This generates a period dT during which both the output signal G(n) and the subsequent output signal G(n+1) are made to have a high level. This may bring about erroneous operations or quality deterioration in a device using the shift register 200.